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features tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 external clock prescale (ecp) module high-performance static cmos technology ? programmable low-frequency external clock (clk) tms470r1x 16/32-bit risc core ( arm7tdmi?) seven communication interfaces: ? 24-mhz system clock (60-mhz pipeline ? three serial peripheral interfaces (spis) mode) 255 programmable baud rates ? independent 16/32-bit instruction set ? two serial communications interfaces ? open architecture with third-party support (scis) ? built-in debug module 2 24 selectable baud rates ? utilizes big-endian format asynchronous/isosynchronous modes integrated memory two high-end can controllers (heccs) ? 512k-byte program flash 32-mailbox capacity each 2 banks with 14 contiguous sectors fully compliant with can protocol, version 2.0b internal state machine for programming and erase high-end timer (het) ? 32k-byte static ram (sram) ? 32 programmable i/o channels: 27 dedicated general-purpose input/output 24 high-resolution pins (gio) pins, 1 input-only gio pin, and 59 8 standard-resolution pins additional peripheral i/os ? high-resolution share feature (xor) operating features ? high-end timer ram ? core supply voltage (v cc ): 1.81 v ? 2.05 v 128-instruction capacity ? i/o supply voltage (v ccio ): 3.0 v ? 3.6 v 16-channel 10-bit multi-buffered adc ? low-power modes: standby and halt (mibadc) ? extended industrial temperature range ? 128-word fifo buffer 470+ system module ? single- or continuous-conversion modes ? 32-bit address space decoding ? 1.55 m s minimum sample and conversion ? bus supervision for memory and time peripherals ? calibration mode and self-test features ? analog watchdog (awd) timer eight external interrupts ? real-time interrupt (rti) flexible interrupt handling ? system integrity and failure detection on-chip scan-base emulation logic, ieee ? interrupt expansion module (iem) standard 1149.1 (1) (jtag) test-access port direct memory access (dma) controller 144-pin plastic low-profile quad flatpack (pge suffix) ? 32 control packets and 16 channels (1) the test-access port is compatible with the ieee standard zero-pin phase-locked loop (zpll)-based 1149.1-1990, ieee standard test-access port and boundary clock module with prescaler scan architecture specification. boundary scan is not ? multiply-by-4 or -8 internal zpll option supported on this device. ? zpll bypass mode please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. arm7tdmi is a trademark of advanced risc machines limited (arm). all other trademarks are the property of their respective owners. advance information concerns new products in the sampling copyright ? 2005?2006, texas instruments incorporated or preproduction phase of development. characteristic data and other specifications are subject to change without notice. www .ti.com adv ance informa tion
tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 tms470r1b512 144-pin pge package (top view) a. gioa[0]/int0 (pin 39) is an input-only gio pin. 2 submit documentation feedback www .ti.com adv ance informa tion awd het[18] het[20] het[19] spi2ena spi2scs het[22] het[21]giob[1] can2hrx giob[3]giob[2] giob[4] spi2clk spi2simo spi2somigioa[3]/int[3] gioa[2]/int[2] het[31] giob[0] sci2txsci2rx sci2clk het[29]het[28] het[30] v ssio het[24] v ccio v ss v cc can2htxgioa[0]/int[0] (a) trst test gioa[1]/int[1]/eclk 7271 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 adin[11] adin[14]adin[10] adin[13] adin[9] adin[12] adin[8] ad refhi ad reflo v ccad v ssad tms tms2 gioc[0] het[23]het[25] het[26] het[27] v ss v cc het[0]het[1] v ss v cc fltp2 fltp1 v ccp v ss het[2] het[3]het[4] het[5] het[6] het[7] gioc[1]gioc[2] adin[0] adin[1] adin[2] adin[3] adin[4] adin[15] adin[5] adin[6] adin[7] adevt spi3ena spi3scs spi3simo spi3somi spi3clk v cc v ss sci1tx sci1clk can1htx can1hrx v cc v ss giob[7] clkout v ccio v ssio het[9] het[8] giob[6] giob[5] tck tdo tdi plldis 108107 106 105 104 103 102 101 100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 1 2 3 4 5 6 7 8 9 spi1ena spi1scs spi1simospi1somi spi1clk gioc[3]gioc[4] gioc[5] gioc[6] 10 11 12 13 14 15 16 17 18 19 20 21 gioc[7] v ss oscout oscin v cc rst v ssio v ccio giod[3]giod[2] giod[1] giod[0] 22 23 24 25 26 27 28 29 30 31 32 33 het[17]het[16] het[15] het[14] het[13] het[12] het[11] het[10] v ss v cc porrst gioa[7]/int[7] 34 35 36 gioa[6]/int[6] gioa[5]/int[5]gioa[4]/int[4] sci1rx
description tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 the tms470r1b512 (1) device is a member of the texas instruments (ti) tms470r1x family of general-purpose16/32-bit reduced instruction set computer (risc) microcontrollers. the b512 microcontroller offers high performance utilizing the high-speed arm7tdmi 16/32-bit risc central processing unit (cpu), resulting in a high instruction throughput while maintaining greater code efficiency. the arm7tdmi 16/32-bit risc cpu views memory as a linear collection of bytes numbered upwards from zero. the b512 utilizes the big-endian format, where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. high-end embedded control applications demand more performance from their controllers while maintaining low costs. the b512 risc core architecture offers solutions to these performance and cost demands while maintaining low power consumption. the b512 device contains the following: arm7tdmi 16/32-bit risc cpu tms470r1x system module (sys) with 470+ enhancements [including an interrupt expansion module (iem) and a 16-channel direct-memory access (dma) controller] 512k-byte flash 32k-byte sram zero-pin phase-locked loop (zpll) clock module analog watchdog (awd) timer real-time interrupt ( rti) module three serial peripheral interface (spi) modules two serial communications interface (sci) modules two high-end can controller (hecc) modules 10-bit multi-buffered analog-to-digital converter (mibadc) with 16 input channels high-end timer (het) controlling 32 i/os external clock prescale (ecp) module up to 86 i/o pins and 1 input-only pin the functions performed by the 470+ system module (sys) include: address decoding memory protection memory and peripherals bus supervision reset and abort exception management expanded interrupt capability with prioritization for all internal interrupt sources device clock control direct-memory access (dma) and control parallel signature analysis (psa). this data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. for a more detailed functional description of the sys module, see the tms470r1x system module reference guide (literature number spnu189). for a more detailed functional description of the iem module, see the tms470r1x interrupt expansion module (iem) reference guide (literature number spnu211). for a more detailed functional description of the dma module, see the tms470r1x direct memory access (dma) controller reference guide (literature number spnu194). the b512 memory includes general-purpose sram supporting single-cycle read/write accesses in byte, half-word, and word modes. (1) the tms470r1b512 device name will be referred to as either the full device name or as b512 throughout the remainder of this document. 3 submit documentation feedback adv ance informa tion www .ti.com
tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 the flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. the flash operates with a system clock frequency of up to 24 mhz. when in pipeline mode, the flash operates with a system clock frequency of up to 60 mhz. for more detailed information on the f05 devices flash, see the f05 flash section of this data sheet and the tms470r1x f05 flash reference guide (literature number spnu213). the b512 device has seven communication interfaces: three spis, two scis, and two heccs. the spi provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. the sci is a full-duplex, serial i/o interface intended for asynchronous communication between the cpu and other peripherals using the standard non-return-to-zero (nrz) format. the hecc uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (mbps). the hecc is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. for more detailed functional information on the spi, sci, and hecc peripherals, see the specific reference guides (literature numbers spnu195, spnu196, and spnu197, respectively). the het is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. the timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached i/o port. the het can be used for compare, capture, or general-purpose i/o. it is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. for more detailed functional information on the het, see the tms470r1x high-end timer (het) reference guide (literature number spnu199). the b512 het peripheral contains the xor-share feature. this feature allows two adjacent het high- resolution channels to be xored together, making it possible to output smaller pulses than a standard het. for more detailed information on the het xor-share feature, see the tms470r1x high-end timer (het) reference guide (literature number spnu199). the b512 device has a 10-bit-resolution, 16-channel sample-and-hold mibadc. the mibadc channels can be converted individually or can be grouped by software for sequential conversion sequences. there are three separate groupings, two of which can be triggered by an external event. each sequence can be converted once when triggered or configured for continuous conversion mode. for more detailed functional information on the mibadc, see the tms470r1x multi-buffered analog-to-digital converter (mibadc) reference guide (literature number spnu206). the zero-pin phase-locked loop (zpll) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1-8). the function of the zpll is to multiply the external frequency reference to a higher frequency for internal use. the zpll provides aclk to the system (sys) module. the sys module subsequently provides system clock (sysclk), real-time interrupt clock (rticlk), cpu clock (mclk), and peripheral interface clock (iclk) to all other b512 device modules. for more detailed functional information on the zpll, see the tms470r1x zero-pin phase-locked loop (zpll) clock module reference guide (literature number spnu212). note: aclk should not be confused with the mibadc internal clock, adclk. aclk is the continuous system clock from an external resonator/crystal reference. the b512 device also has an external clock prescaler (ecp) module that when enabled, outputs a continuous external clock (eclk) on a specified gio pin. the eclk frequency is a user-programmable ratio of the peripheral interface clock (iclk) frequency. for more detailed functional information on the ecp, see the tms470r1x external clock prescaler (ecp) reference guide (literature number spnu202). 4 submit documentation feedback www .ti.com adv ance informa tion
device characteristics tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 the b512 device is a derivative of the f05 system emulation device se470r1vb8ad. table 1 identifies all the characteristics of the b512 device except the system and cpu, which are generic. table 1. device characteristics device description characteristics comments tms470r1b512 memory for the number of memory selects on this device, see table 3 , memory selection assignment. pipeline/non-pipeline flash is pipeline-capable. internal memory 512k-byte flash the b512 ram is implemented in one 32k array selected by two 32k-byte sram memory-select signals (see table 3 , memory selection assignment). peripherals for the device-specific interrupt priority configurations, see table 7 , interrupt priority (iem and cim). and for the 1k peripheral address ranges and their peripheral selects, see table 5 , a512 peripherals, system module, and flash base addresses. clock zpll zero-pin pll has no external loop filter pins. 27 i/o ports a, b, and c each have eight (8) external pins. general-purpose i/os 1 input only port d has four (4) external pins. ecp yes sci 2 (3-pin) sci1 and sci2 can 2 heccs two high-end can controller modules (hecc1 and hecc2) (hecc and/or scc) spi 3 (5-pin) spi1, spi2, and spi3 (5-pin, 4-pin or 3-pin) the b512 device has both the logic and registers for a full 32-i/o het implemented and all 32 pins are available externally. the high-resolution (hr) share feature allows even hr pins to share the next higher odd hr pin structures. this hr sharing is independent het with xor share 32 i/o of whether or not the odd pin is available externally. if an odd pin is available externally and shared, then the odd pin can only be used as a general-purpose i/o. for more information on hr share, see the tms470r1x high-end timer (het) reference guide (literature number spnu199). het ram 128-instruction capacity mibadc 10-bit, 16-channel 128-word the b512 device has both the logic and registers for a full 16-channel fifo mibadc implemented and all 16 pins are available externally. core voltage 1.81 ? 2.05 v i/o voltage 3.0 ? 3.6 v pins 144 package pge 5 submit documentation feedback adv ance informa tion www .ti.com
tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 functional block diagram a. gioa[0]/int0 is an input-only pin. 6 submit documentation feedback www .ti.com oscinoscout plldis crystal het with xor share (128?word) adin[15:0]adevt ad refhi ad reflo v ccad v ssad mibadc with 128?word fifo zpll het [31:24]het[23:0] hecc1 can1htxcan1hrx can2hrx can2htx hecc2 sci1 sci1clksci1tx sci1rx sci2rx sci2tx sci2clk sci2 spi1 spi2 gio spi3 ecp expansion address/data bus flash (512k bytes) 14 sectors (32k bytes) ram tms470r1x cpu tms470r1x system module dma controller 16 channels interrupt expansion module (iem) v ccp fltp1 fltp2 trst tck tdi tdotms tms2 rst awd test porrst clkout gioa[1]/int[1]/ eclk int[2:7] gioa[2:7]/ gioa[0]/int[0] (a) spi3clk spi3somi spi3simo spi3ena spi3scs spi2scs spi2clk spi2somi spi2simo spi2ena spi1clk spi1somi spi1simo spi1ena spi1scs external pins external pins cpu address/data bus giob[0:7]gioc[0:7] giod[0:3] adv ance informa tion
tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 table 2. terminal functions terminal internal type (1) (2) pullup/ description name no. pulldown (3) high-end timer (het) het[0] 129 het[1] 130 het[2] 137 het[3] 138 het[4] 139 het[5] 140 het[6] 141 het[7] 142 het[8] 79 het[9] 80 het[10] 29 het[11] 28 the b512 device has both the logic and registers for a full 32-i/o het het[12] 27 implemented and all 32 pins are available externally. het[13] 26 timer input capture or output compare. the het[31:0] applicable pins can be programmed as general-purpose input/output (gio) pins. het[23:0] are het[14] 25 high-resolution pins and het[31:24] are standard-resolution pins. het[15] 24 the high-resolution (hr) share feature allows even hr pins to share the 3.3-v i/o ipd (20 m a) het[16] 23 next higher odd hr pin structures. this hr sharing is independent of whether or not the odd pin is available externally. if an odd pin is available het[17] 22 externally and shared, then the odd pin can only be used as a het[18] 71 general-purpose i/o. for more information on hr share, see the tms470r1x high-end timer (het) reference guide (literature number het[19] 70 spnu199). het[20] 69 het[21] 68 het[22] 67 het[23] 123 het[24] 51 het[25] 124 het[26] 125 het[27] 126 het[28] 47 het[29] 48 het[30] 49 het[31] 50 high-end can controller 1 (hecc1) can1htx 88 3.3-v i/o ipu (20 m a) hecc1 transmit pin or gio pin can1hrx 87 3.3-v i/o hecc1 receive pin or gio pin high-end can controller 2 (hecc2) can2htx 56 3.3-v i/o ipu (20 m a) hecc2 transmit pin or gio pin can2hrx 57 3.3-v i/o hecc2 receive pin or gio pin (1) i = input, o = output, pwr = power, gnd = ground, ref = reference voltage, nc = no connect (2) all i/o pins, except rst, are configured as inputs while porrst is low and immediately after porrst goes high. (3) ipd = internal pulldown, ipu = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the porrst state.) 7 submit documentation feedback adv ance informa tion www .ti.com
tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 table 2. terminal functions (continued) terminal internal type (1) (2) pullup/ description name no. pulldown (3) general-purpose i/o (gio) gioa[0]/int0 39 3.3-v i gioa[1]/int1/ 40 eclk gioa[2]/int2 41 gioa[3]/int3 42 gioa[4]/int4 36 gioa[5]/int5 35 gioa[6]/int6 34 gioa[7]/int7 33 giob[0] 46 giob[1] 58 giob[2] 59 giob[3] 60 general-purpose input/output pins. giob[4] 61 gioa[0]/int[0] is an input-only pin. gioa[7:0]/int[7:0] are giob[5] 77 ipd (20 m a) interrupt-capable pins. 3.3-v i/o giob[6] 78 the gioa[1]/int[1]/eclk pin is multiplexed with the external clock-out function of the external clock prescale (ecp) module. giob[7] 84 gioc[0] 122 gioc[1] 143 gioc[2] 144 gioc[3] 6 gioc[4] 7 gioc[5] 8 gioc[6] 9 gioc[7] 10 giod[0] 21 giod[1] 20 giod[2] 19 giod[3] 18 multi-buffered analog-to-digital converter (mibadc) adevt 99 3.3-v i/o ipd (20 m a) mibadc event input. adevt can be programmed as a gio pin. adin[0] 108 adin[1] 107 adin[2] 106 adin[3] 105 adin[4] 104 adin[5] 102 adin[6] 101 3.3-v i mibadc analog input pins adin[7] 100 adin[8] 115 adin[9] 113 adin[10] 111 adin[11] 109 adin[12] 114 8 submit documentation feedback www .ti.com adv ance informa tion
tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 table 2. terminal functions (continued) terminal internal type (1) (2) pullup/ description name no. pulldown (3) multi-buffered analog-to-digital converter (mibadc) (continued) adin[13] 112 adin[14] 110 3.3-v i mibadc analog input pins adin[15] 103 ad refhi 116 3.3-v ref i mibadc module high-voltage reference input ad reflo 117 gnd ref i mibadc module low-voltage reference input v ccad 118 3.3-v pwr mibadc analog supply voltage v ssad 119 gnd mibadc analog ground reference serial peripheral interface 1 (spi1) spi1clk 5 spi1 clock. spi1clk can be programmed as a gio pin. spi1ena 1 spi1 chip enable. spi1ena can be programmed as a gio pin. spi1scs 2 spi1 slave chip select. spi1scs can be programmed as a gio pin. 3.3-v i/o ipd (20 m a) spi1 data stream. slave in/master out. spi1simo can be programmed as spi1simo 3 a gio pin. spi1 data stream. slave out/master in. spi1somi can be programmed as spi1somi 4 a gio pin. serial peripheral interface 2 (spi2) spi2clk 62 spi2 clock. spi2clk can be programmed as a gio pin. spi2ena 65 spi2 chip enable. spi2ena can be programmed as a gio pin. spi2scs 66 spi2 slave chip select. spi2scs can be programmed as a gio pin. 3.3-v i/o ipd (20 m a) spi2 data stream. slave in/master out. spi2simo can be programmed as spi2simo 63 a gio pin. spi2 data stream. slave out/master in. spi2somi can be programmed as spi2somi 64 a gio pin. serial peripheral interface 3 (spi3) spi3clk 94 spi3 clock. spi3clk can be programmed as a gio pin. spi3ena 98 spi3 chip enable. spi3ena can be programmed as a gio pin. spi3scs 97 spi3 slave chip select. spi3scs can be programmed as a gio pin. 3.3-v i/o ipd (20 m a) spi3 data stream. slave in/master out. spi3simo can be programmed as spi3simo 96 a gio pin. spi3 data stream. slave out/master in. spi3somi can be programmed as spi3somi 95 a gio pin. zero-pin phase-locked loop (zpll) oscin 13 1.8-v i crystal connection pin or external clock input oscout 12 1.8-v o external crystal connection pin enable/disable the zpll. the zpll can be bypassed and the oscillator becomes the system clock. if not in bypass mode, ti recommends that this plldis 73 3.3-v i ipd (20 m a) pin be connected to ground or pulled down to ground by an external resistor. serial communications interface 1 (sci1) sci1clk 89 3.3-v i/o ipd (20 m a) sci1 clock. sci1clk can be programmed as a gio pin. sci1rx 91 3.3-v i/o ipu (20 m a) sci1 data receive. sci1rx can be programmed as a gio pin. sci1tx 90 3.3-v i/o ipu (20 m a) sci1 data transmit. sci1tx can be programmed as a gio pin. serial communications interface 2 (sci2) sci2clk 45 3.3-v i/o ipd (20 m a) sci2 clock. sci2clk can be programmed as a gio pin. sci2rx 43 3.3-v i/o ipu (20 m a) sci2 data receive. sci2rx can be programmed as a gio pin. sci2tx 44 3.3-v i/o ipu (20 m a) sci2 data transmit. sci2tx can be programmed as a gio pin. 9 submit documentation feedback adv ance informa tion www .ti.com
tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 table 2. terminal functions (continued) terminal internal type (1) (2) pullup/ description name no. pulldown (3) system module (sys) bidirectional pin. clkout can be programmed as a gio pin or the output clkout 83 3.3-v i/o ipd (20 m a) of sysclk, iclk, or mclk. input master chip power-up reset. external v cc monitor circuitry must porrst 32 3.3-v i ipd (20 m a) assert a power-on reset. bidirectional reset. the internal circuitry can assert a reset, and an external system reset can assert a device reset. on this pin, the output buffer is implemented as an open drain (drives low rst 15 3.3-v i/o ipu (20 m a) only). to ensure an external reset is not arbitrarily generated, ti recommends that an external pullup resistor be connected to this pin. watchdog/real-time interrupt (wd/rti) analog watchdog reset. the awd pin provides a system reset if the wd key is not written in time by the system, providing an external rc network circuit is connected. awd 72 3.3-v i/o ipd (20 m a) if the user is not using awd, ti recommends that this pin be connected to ground or pulled down to ground by an external resistor. for more details on the external rc network circuit, see the tms470r1x system module reference guide (literature number spnu189). test/debug (t/d) tck 76 3.3-v i ipd (20 m a) test clock. tck controls the test hardware (jtag). test data in. tdi inputs serial data to the test instruction register, test data tdi 74 3.3-v i ipu (20 m a) register, and programmable test address (jtag). test data out. tdo outputs serial data from the test instruction register, tdo 75 3.3-v o ipd (20 m a) test data register, identification register, and programmable test address (jtag). test enable. reserved for internal use only. ti recommends that this pin test 38 3.3-v i ipd (20 m a) be connected to ground or pulled down to ground by an external resistor. serial input for controlling the state of the cpu test access port (tap) tms 120 3.3-v i ipu (20 m a) controller (jtag) serial input for controlling the second tap. ti recommends that this pin be tms2 121 3.3-v i ipu (20 m a) connected to vccio or pulled up to vccio by an external resistor. test hardware reset to tap1 and tap2. ieee standard 1149-1 (jtag) trst 37 3.3-v i ipd (20 m a) boundary-scan logic. ti recommends that this pin be pulled down to ground by an external resistor. flash flash test pad 1. for proper operation, this pin must not be connected fltp1 134 nc [no connect (nc)]. flash test pad 2. for proper operation, this pin must not be connected fltp2 133 nc [no connect (nc)]. flash external pump voltage (3.3 v). this pin is required for both flash v ccp 135 3.3-v pwr read and flash program and erase operations. supply voltage core (1.8 v) 14 31 55 v cc 86 1.8-v pwr core logic supply voltage 93 128 132 10 submit documentation feedback www .ti.com adv ance informa tion
tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 table 2. terminal functions (continued) terminal internal type (1) (2) pullup/ description name no. pulldown (3) supply voltage digital i/o (3.3 v) 17 v ccio 53 3.3-v pwr digital i/o supply voltage 82 supply ground core 11 30 54 85 v ss gnd core supply ground reference 92 127 131 136 supply ground digital i/o 16 v ssio 52 gnd digital i/o supply ground reference 81 11 submit documentation feedback adv ance informa tion www .ti.com
b512 device-specific information memory tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 figure 1 shows the memory map of the b512 device. a. memory addresses are configurable by the system (sys) module within the range of 0x0000_0000 to 0xffe0_0000. b. the cpu registers are not a part of the memory map. figure 1. memory map 12 submit documentation feedback www .ti.com fiq irq reserved data abort prefetch abort software interrupt undefined instruction reset system module (512k bytes) (512k bytes) peripheral control registers reserved flash control registers reserved mpu control registers reserved program and data area exception, interrupt, and reset v ectors system with psa, cim, rti, dec, dma, mmc iem reserved het spi1 sci2sci1 mibadc gio/ecp hecc1/hecc2 hecc1/2 ram reserved spi2/spi3 reservedreserved ram (32k bytes) flash (512k bytes) 14 sectors memory (4g bytes) 0xffff_ffff 0xfff8_0000 0xfff7_ffff 0xfff0_0000 0xffe8_c000 0xffe8_bfff 0xffe8_8000 0xffe8_7fff 0xffe8_40240xffe8_4023 0xffe8_4000 0xffe8_3fff 0xffe0_0000 0x0000_00200x0000_001f 0x0000_0000 0xffff_ffff0xffff_fd00 0xffff_fc00 0xfff8_0000 0xfff7_fc00 0xfff7_f800 0xfff7_f500 0xfff7_f400 0xfff7_f000 0xfff7_ec00 0xfff7_e800 0xfff7_d400 0xfff7_e4000xfff7_d800 0xfff0_0000 0xfff7_c0000x0000_0018 0x0000_001c0x0000_0014 0x0000_0010 0x0000_000c 0x0000_0008 0x0000_0004 0x0000_0000 0xffef_ffff 0x0000_001f control registers het ram (1.5k bytes) adv ance informa tion
memory selects tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 memory selects allow the user to address memory arrays (i.e., flash, ram, and het ram) at user-defined addresses. each memory select has its own set (low and high) of memory base address registers (mfbahrx and mfbalrx) that, together, define the array's starting (base) address, block size, and protection. the base address of each memory select is configurable to any memory address boundary that is a multiple of the decoded block size. for more information on how to control and configure these memory select registers, see the bus structure and memory sections of the tms470r1x system module reference guide (literature number spnu189). for the memory selection assignments and the memory selected, see table 3 . table 3. memory selection assignment memory memory selected memory memory base address static mem mpu select (all internal) size register ctl register 0 (fine) flash no mfbahr0 and mfbalr0 512k 1 (fine) flash no mfbahr1 and mfbalr1 2 (fine) ram yes mfbahr2 and mfbalr2 32k (1) 3 (fine) ram yes mfbahr3 and mfbalr3 4 (fine) het ram 1.5k mfbahr4 and mfbalr4 smcr1 (1) the starting addresses for both ram memory-select signals cannot be offset from each other by a multiple of the user-defined block size in the memory-base address register. ram the b512 device contains 32k bytes of internal static ram configurable by the sys module to be addressed within the range of 0x0000_0000 to 0xffe0_0000. this b512 ram is implemented in one 32k array selected by two memory-select signals. this b512 configuration imposes an additional constraint on the memory map for ram; the starting addresses for both ram memory selects cannot be offset from each other by the multiples of the size of the physical ram (i.e., 32k for the b512 device). the b512 ram is addressed through memory selects 2 and 3. the ram can be protected by the memory protection unit (mpu) portion of the sys module, allowing the user finer blocks of memory protection than is allowed by the memory selects. the mpu is ideal for protecting an operating system while allowing access to the current task. for more detailed information on the mpu portion of the sys module and memory protection, see the memory section of the tms470r1x system module reference guide (literature number spnu189). f05 flash the f05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. the f05 flash has an external state machine for program and erase functions. see the flash read and flash program and erase sections below. for more detailed functional information on the f05 flash module, see the tms470r1x f05 flash reference guide (literature number spnu213). flash protection keys the b512 device provides flash protection keys. these four 32-bit protection keys prevent program/erase/compaction operations from occurring until after the four protection keys have been matched by the cpu loading the correct user keys into the fmpkey control register. the protection keys on the b512 are located in the last 4 words of the first 16k sector. for more detailed information on the flash protection keys and the fmpkey control register, see the "optional quadruple protection keys" and "programming the protection keys" portions of the tms470r1x f05 flash reference guide (literature number spnu213). 13 submit documentation feedback adv ance informa tion www .ti.com
tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 flash read the b512 flash memory is configurable by the sys module to be addressed within the range of 0x0000_0000 to 0xffe0_0000. the flash is addressed through memory selects 0 and 1. note: the flash external pump voltage (v ccp ) is required for all operations (program, erase, and read). flash pipeline mode when in pipeline mode, the flash operates with a system clock frequency of up to 60 mhz. in normal mode, the flash operates with a system clock frequency in normal mode of up to 24 mhz. flash in pipeline mode is capable of accessing 64-bit words and provides two 32-bit pipelined words to the cpu. also in pipeline mode, the flash can be read with no wait states when memory addresses are contiguous (after the initial 1-or 2-wait-state reads). note: after a system reset, pipeline mode is disabled (fmregopt[0] = 0). in other words, the b512 device powers up and comes out of reset in non-pipeline mode. furthermore, setting the flash configuration mode bit (gblctrl[4]) will override pipeline mode. flash program and erase the b512 device flash contains two 256k-byte memory arrays (or banks) for a total of 512k bytes of flash and consists of fourteen sectors. these fourteen sectors are sized as follows: table 4. b512 flash memory banks and sectors memory arrays sector no. segment low address high address (or banks) 0 16k bytes 0x00000000 0x00003fff 1 16k bytes 0x00004000 0x00007fff 2 32k bytes 0x00008000 0x0000ffff 3 32k bytes 0x00010000 0x00017fff 4 32k bytes 0x00018000 0x0001ffff bank0 (256k bytes) 5 32k bytes 0x00020000 0x00027fff 6 32k bytes 0x00028000 0x0002ffff 7 32k bytes 0x00030000 0x00037fff 8 16k bytes 0x00038000 0x0003bfff 9 16k bytes 0x0003c000 0x0003ffff 0 64k bytes 0x00040000 0x0004ffff 1 64k bytes 0x00050000 0x0005ffff bank1 (256k bytes) 2 64k bytes 0x00060000 0x0006ffff 3 64k bytes 0x00070000 0x0007ffff the minimum size for an erase operation is one sector. the maximum size for a program operation is one 16-bit word. note: the flash external pump voltage (v ccp ) is required for all operations (program, erase, and read). for more detailed information on flash program and erase operations, see the tms470r1x f05 flash reference guide (literature number spnu213). 14 submit documentation feedback www .ti.com adv ance informa tion
peripheral selects and base addresses tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 het ram the b512 device contains het ram. the het ram has a 128-instruction capability. the het ram is configurable by the sys module to be addressed within the range of 0x0000_0000 to 0xffe0_0000. the het ram is addressed through memory select 4. the b512 device uses 8 of the 16 peripheral selects to decode the base addresses of the peripherals. these peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used by the sys module. control registers for the peripherals, sys module, and flash begin at the base addresses shown in table 5 . table 5. b512 peripherals, system module, and flash base addresses address range connecting module peripheral selects base address ending address system 0 x ffff_ffd0 0 x ffff_ffff n/a reserved 0 x ffff_ff60 0 x ffff_ffcf n/a psa 0 x ffff_ff40 0 x ffff_ff5f n/a cim 0 x ffff_ff20 0 x ffff_ff3f n/a rti 0 x ffff_ff00 0 x ffff_ff1f n/a dma 0 x ffff_fe80 0 x ffff_feff n/a dec 0 x ffff_fe00 0 x ffff_fe7f n/a mmc 0 x ffff_fd00 0 x ffff_fd7f n/a iem 0 x ffff_fc00 0 x ffff_fcff n/a reserved 0 x ffff_fb00 0 x ffff_fbff n/a reserved 0 x ffff_fa00 0 x ffff_faff n/a dma cmd buffer 0 x ffff_f800 0 x ffff_f9ff n/a reserved 0 x fff8_0000 0 x ffff_f7ff n/a reserved 0 x fff7_fd00 0 x fff7_ffff ps[0] het 0 x fff7_fc00 0 x fff7_fcff reserved 0 x fff7_f900 0 x fff7_fbff ps[1] spi1 0 x fff7_f800 0 x fff7_f8ff reserved 0 x fff7_f600 0 x fff7_f7ff sci2 0 x fff7_f500 0 x fff7_f5ff ps[2] sci1 0 x fff7_f400 0 x fff7_f4ff reserved 0 x fff7_f100 0 x fff7_f3ff ps[3] mibadc 0 x fff7_f000 0 x fff7_f0ff ecp 0 x fff7_ef00 0 x fff7_efff reserved 0 x fff7_ed00 0 x fff7_eeff ps[4] gio 0 x fff7_ec00 0 x fff7_ecff hecc2 0 x fff7_ea00 0 x fff7_ebff ps[5] hecc1 0 x fff7_e800 0 x fff7_e9ff hecc2 ram 0 x fff7_e600 0 x fff7_e7ff ps[6] hecc1 ram 0 x fff7_e400 0 x fff7_e5ff reserved 0 x fff7_e000 0 x fff7_e3ff ps[7] reserved 0 x fff7_dc00 0 x fff7_dfff ps[8] reserved 0 x fff7_d800 0 x fff7_dbff ps[9] reserved 0 x fff7_d600 0 x fff7_d7ff spi3 0 x fff7_d500 0 x fff7_d5ff ps[10] spi2 0 x fff7_d400 0 x fff7_d4ff reserved 0 x fff7_c000 0 x fff7_d3ff ps[11] ? ps[15] 15 submit documentation feedback adv ance informa tion www .ti.com
direct-memory access (dma) tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 table 5. b512 peripherals, system module, and flash base addresses (continued) address range connecting module peripheral selects base address ending address reserved 0 x fff0_0000 0 x fff7_bfff n/a flash control registers 0 x ffe8_8000 0 x ffe8_bfff n/a mpu control registers 0 x ffe8_4000 0 x ffe8_4023 n/a the direct-memory access (dma) controller transfers data to and from any specified location in the b512 memory map (except for restricted memory locations like the system control registers area). the dma manages up to 16 channels, and supports data transfer for both on-chip and off-chip memories and peripherals. the dma controller is connected to both the cpu and peripheral busses, enabling these data transfers to occur in parallel with cpu activity and thus, maximizing overall system performance. although the dma controller has two possible configurations, for the b512 device, the dma controller configuration is 32 control packets and 16 channels. for the b512 dma request hardwired configuration, see table 6 . for a more detailed functional description of the dma module, see the tms470r1x direct memory access (dma) controller reference guide (literature number spnu194). table 6. dma request lines connections modules dma request interrupt sources dma channel reserved dmareq[0] spi1 spi1 end-receive spi1dma0 dmareq[1] spi1 spi1 end-transmit spi1dma1 dmareq[2] mibadc (1) mibadc event mibadcdma0 dmareq[3] mibadc (1) /sci1 mibadc g1/sci1 end-receive mibadcdma1/sci1dma0 dmareq[4] mibadc (1) /sci1 mibadc g2/sci1 end-transmit mibadcdma2/sci1dma1 dmareq[5] reserved dmareq[6] spi2 spi2 end-receive spi2dma0 dmareq[7] spi2 spi2 end-transmit spi2dma1 dmareq[8] reserved dmareq[9] reserved dmareq[10] reserved dmareq[11] reserved dmareq[12] reserved dmareq[13] sci2/spi3 sci2 end-receive/spi3 end-receive sci2dma0/spi3dma0 dmareq[14] sci2/spi3 sci2 end-transmit/spi3 end-transmit sci2dma1/spi3dma1 dmareq[15] (1) the mibadc is capable of being serviced by the dma when the device is in buffered mode. for more information on buffered mode, see the mibadc section of this data sheet and the tms470r1x multi-buffered analog-to-digital converter (mibadc) reference guide (literature number spnu206). each channel has two control packets attached to it, allowing the dma to continuously load ram and generate periodic interrupts so that the data can be read by the cpu. the control packets allow for the interrupt enable, and the channels determine the priority level of the interrupt. dma transfers occur in one of two modes: non-request mode (used when transferring from memory to memory) request mode (used when transferring from memory to peripheral) for more detailed functional information on the dma controller, see the tms470r1x direct memory access (dma) controller reference guide (literature number spnu194). 16 submit documentation feedback www .ti.com adv ance informa tion
interrupt priority (iem to cim) tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 interrupt requests originating from the b512 peripheral modules (i.e., spi1, spi2, or spi3; sci1 or sci2; hecc1 or hecc2; rti; etc.) are assigned to channels within the 48-channel interrupt expansion module (iem) where, via programmable register mapping, these channels are then mapped to the 32-channel central interrupt manager (cim) portion of the sys module. programming multiple interrupt sources in the iem to the same cim channel effectively shares the cim channel between sources. the cim request channels are maskable so that individual channels can be selectively disabled. all interrupt requests can be programmed in the cim to be of either type: fast interrupt request (fiq) normal interrupt request (irq) the cim prioritizes interrupts. the precedence of request channels decrease with ascending channel order in the cim (0 [highest] and 31 [lowest] priority). for iem-to-cim default mapping, channel priorities, and their associated modules, see table 7 . table 7. interrupt priority (iem and cim) default cim interrupt modules interrupt sources iem channel level/channel spi1 spi1 end-transfer/overrun 0 0 rti comp2 interrupt 1 1 rti comp1 interrupt 2 2 rti tap interrupt 3 3 spi2 spi2 end-transfer/overrun 4 4 gio gio interrupt a 5 5 reserved 6 6 het het interrupt 1 7 7 reserved 8 8 sci1/sci2 sci1 or sci2 error interrupt 9 9 sci1 sci1 receive interrupt 10 10 reserved 11 11 reserved 12 12 hecc1 hecc1 interrupt a 13 13 reserved 14 14 spi3 spi3 end-transfer/overrun 15 15 mibadc mibadc end event conversion 16 16 sci2 sci2 receive interrupt 17 17 dma dma interrupt 0 18 18 reserved 19 19 sci1 sci1 transmit interrupt 20 20 system sw interrupt (ssi) 21 21 reserved 22 22 het het interrupt 2 23 23 hecc1 hecc1 interrupt b 24 24 reserved 25 25 sci2 sci2 transmit interrupt 26 26 mibadc mibadc end group 1 conversion 27 27 dma dma interrupt 1 28 28 gio gio interrupt b 29 29 mibadc mibadc end group 2 conversion 30 30 reserved 31 31 17 submit documentation feedback adv ance informa tion www .ti.com
tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 table 7. interrupt priority (iem and cim) (continued) default cim interrupt modules interrupt sources iem channel level/channel reserved 31 32 reserved 31 33 reserved 31 34 reserved 31 35 reserved 31 36 reserved 31 37 hecc2 hecc2 interrupt a 31 38 hecc2 hecc2 interrupt b 31 39 reserved 31 40 reserved 31 41 reserved 31 42 reserved 31 43 reserved 31 44 reserved 31 45 reserved 31 46 reserved 31 47 for more detailed functional information on the iem, see the tms470r1x interrupt expansion module (iem) reference guide (literature number spnu211). for more detailed functional information on the cim, see the tms470r1x system module reference guide (literature number spnu189). 18 submit documentation feedback www .ti.com adv ance informa tion
mibadc tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 the multi-buffered analog-to-digital converter (mibadc) accepts an analog signal and converts the signal to a 10-bit digital value. the b512 mibadc module can function in two modes: compatibility mode, where its programmer's model is compatible with the tms470r1x adc module and its digital results are stored in digital result registers; or in buffered mode, where the digital result registers are replaced with three fifo buffers, one for each conversion group [event, group1 (g1), and group2 (g2)]. in buffered mode, the mibadc buffers can be serviced by interrupts or by the dma. mibadc event trigger enhancements the mibadc includes two major enhancements over the event-triggering capability of the tms470r1x adc. both group1 and the event group can be configured for event-triggered operation, providing up to two event-triggered groups. the trigger source and polarity can be selected individually for both group 1 and the event group from the three options identified in table 8 . table 8. mibadc event hookup configuration source select bits for g1 or event event no. signal pin name (g1src[1:0] or evsrc[1:0]) event1 00 adevt event2 01 het18 event3 10 het19 event4 11 reserved for group 1, these event-triggered selections are configured via the group 1 source select bits (g1src[1:0]) in the ad event source register (adevtsrc[5:4]). for the event group, these event-triggered selections are configured via the event group source select bits (evsrc[1:0]) in the ad event source register (adevtsrc[1:0]). for more detailed functional information on the mibadc, see the tms470r1x multi-buffered analog-to-digital converter (mibadc) reference guide (literature number spnu206). 19 submit documentation feedback adv ance informa tion www .ti.com
documentation support tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 extensive documentation supports all of the tms470 microcontroller family generation of devices. the types of documentation available include: data sheets with design specifications; complete user's guides for all devices and development support tools; and hardware and software applications. useful reference documentation includes: bulletin ? tms470 microcontroller family product bulletin (literature number spnb086) user's guides ? tms470r1x system module reference guide (literature number spnu189) ? tms470r1x general purpose input/output (gio) reference guide (literature number spnu192) ? tms470r1x direct memory access (dma) controller reference guide (literature number spnu194) ? tms470r1x serial peripheral interface (spi) reference guide (literature number) spnu195 ? tms470r1x serial communication interface (sci) reference guide (literature number spnu196) ? tms470r1x controller area network (can) reference guide (literature number spnu197) ? tms470r1x high end timer (het) reference guide (literature number spnu199) ? tms470r1x external clock prescale (ecp) reference guide (literature number spnu202) ? tms470r1x multibuffered analog to digital (mibadc) reference guide (literature number spnu206) ? tms470r1x zeropin phase locked loop (zpll) clock module reference guide (literature number spnu212) ? tms470r1x f05 flash reference guide (literature number spnu213) ? tms470r1x class ii serial interface b (c2sib) reference guide (literature number spnu214) ? tms470r1x class ii serial interface a (c2sia) reference guide (literature number spnu218) ? tms470r1x jtag security module (jsm) reference guide (literature number spnu245) ? tms470r1x memory security module (msm) reference guide (literature number spnu246) ? tms470 peripherals overview reference guide (literature number spnu248) errata sheet ? tms470r1b512 tms470 microcontrollers silicon errata (literature number spnz141) 20 submit documentation feedback www .ti.com adv ance informa tion
device numbering conventions tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 figure 2 illustrates the numbering and symbol nomenclature for the tms470r1x family. figure 2. tms470r1x family nomenclature 21 submit documentation feedback adv ance informa tion www .ti.com tms 470 r1 b 512 pge prefix tms family 470 architecture r1 device type b = fully qualified device = tms470 risc ? embedded microcontroller family = arm7tdm1 cpu 1.8-v core, 3.3-v i/oflash program memory zpll clock32-byte static ram 1.5k-byte het ram (128 instructions) analog w atchdog (a wd) real-t ime interrupt (r ti) 10-bit, 12-input mibadcthree spi modules three sci modules t wo can [hecc] modules het , 32 channels ecpdma with 512k?bytes flash memory: options p ackage type pge = 144-pin low-profile quad flatpack (lqfp) revision change blank = original flash memor y 512 = 512k-bytes flash memory temperature t = 40 c to 105 c t 60-mhz frequency q = 40 c to 125 c
device identification code register tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 the device identification code register identifies the silicon version, the technology family (tf), a rom or flash device, and an assigned device-specific part number (see figure 3 ). the b512 device identification code register value is 0xn92fh. figure 3. tms470 device id bit allocation register [offset = ffff_fff0h] 31 16 reserved 15 12 11 10 9 3 2 1 0 version tf r/f part number 1 1 1 r-k r-k r-k r-k r-1 r-1 r-1 legend: r = read only, -k = value constant after rst; - n = value after rst table 9. tms470 device id bit allocation register field descriptions bit field value description 31-16 reserved reads are undefined and writes have no effect. 15-12 version silicon version (revision) bits. these bits identify the silicon version of the device. initial device version numbers start at 0000. the current revision for the b512 device is 0010. 11 tf technology family bit. this bit distinguishes the technology family core power supply: 0 3.3 v for f10/c10 devices 1 1.8 v for f05/c05 devices 10 r/f rom/flash bit. this bit distinguishes between rom and flash devices: 0 flash device 1 rom device 9-3 part number device-specific part number bits. these bits identify the assigned device-specific part number. the assigned device-specific part number for the b512 device is 0100101. 2-0 1 mandatory high. bits 2, 1, and 0 are tied high by default. 22 submit documentation feedback www .ti.com adv ance informa tion
device electrical specifications and timing parameters absolute maximum ratings device recommended operating conditions (1) tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 over operating free-air temperature range, t version (unless otherwise noted) (1) supply voltage range: v cc (2) ?0.3 v to 2.5 v supply voltage range: v ccio , v ccad , v ccp (flash pump) (2) ?0.3 v to 4.1v input voltage range: all input pins ?0.3 v to 4.1v input clamp current: i ik (v i < 0 or v i > v ccio ) all pins except adin[0:11], porrst, trst , test, and tck 20 ma i ik (v i < 0 or v i > v ccad ) adin[0:15] 10 ma operating free-air temperature range, t version ?40 c to 105 c t a : q version ?40 c to 125 c operating junction temperature ranges, t j ?40 c to 150 c storage temperature range, t stg ?65 c to 150 c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to their associated grounds. min nom max unit v cc digital logic supply voltage (core) 1.81 2.05 v v ccio digital logic supply voltage (i/o) 3 3.3 3.6 v v ccad mibadc supply voltage 3 3.3 3.6 v v ccp flash pump supply voltage 3 3.3 3.6 v v ss digital logic supply ground 0 v v ssad mibadc supply ground ?0.1 0.1 v t a operating free-air temperature t version ?40 105 c q version ?40 125 t j operating junction temperature ?40 150 c (1) all voltages are with respect to v ss , except v ccad , which is with respect to v ssad . 23 submit documentation feedback adv ance informa tion www .ti.com
electrical characteristics tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 over recommended operating free-air temperature range, t version (unless otherwise noted) (1) parameter test conditions min typ max unit v hys input hysteresis 0.15 v all inputs (2) ?0.3 0.8 except oscin v il low-level input voltage v oscin only ?0.3 0.35 v cc all inputs except 2 v ccio + 0.3 oscin v ih high-level input voltage v oscin only 0.65 v cc v cc + 0.3 v th input threshold voltage awd only 1.35 1.8 v drain to source on rds on awd only (3) v ol = 0.35 v at i ol = 8 ma 45 w resistance i ol = i ol max 0.2 v ccio v ol low-level output voltage (4) v i ol = 50 a 0.2 i oh = i oh min 0.8 v ccio v oh high-level output voltage (4) v i oh = 50 a v ccio ? 0.2 v i < v ssio ? 0.3 or i ic input clamp current (i/o pins) (5) ?2 2 ma v i > v ccio + 0.3 i il pulldown v i = v ss ?1 1 i ih pulldown v i = v ccio 5 40 i i input current (i/o pins) i il pullup v i = v ss ?40 ?5 m a i ih pullup v i = v ccio ?1 1 all other pins no pullup or pulldown ?1 1 clkout, awd, 8 tdo rst, spinclk, i ol low-level output current spinsomi, v ol = v ol max 4 ma spinsimo all other output 2 pins (6) clkout, tdo ?8 rst, spinclk, spinsomi, ?4 i oh high-level output current spinsimo v oh = v oh min ma all other output pins except ?2 rst (6) sysclk = 60 mhz, 125 ma iclk = 20 mhz, v cc = 2.05 v v cc digital supply current (operating mode) sysclk = 24 mhz, 85 ma i cc iclk = 12 mhz, v cc = 2.05 v v cc digital supply current (standby mode) (7) oscin = 6 mhz, v cc = 2.05 v 4 ma v cc digital supply current (halt mode) (7) all frequencies, v cc = 2.05 v 2.0 ma (1) source currents (out of the device) are negative while sink currents (into the device) are positive. (2) this does not apply to the porrst pin. for porrst exceptions, see the rst and porrst timings section. (3) these values help to determine the external rc network circuit. for more details, see the tms470r1x system module reference guide (literature number spnu189). (4) v ol and v oh are linear with respect to the amount of load current (i ol /i oh ) applied. (5) parameter does not apply to input-only or output-only pins. (6) the 2 ma buffers on this device are called zero-dominant buffers. if two of these buffers are shorted together and one is outputting a low level and the other is outputting a high level, the resulting value will always be low. (7) for flash pumps/banks in sleep mode. 24 submit documentation feedback www .ti.com adv ance informa tion
parameter measurement information tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 electrical characteristics (continued) over recommended operating free-air temperature range, t version (unless otherwise noted) parameter test conditions min typ max unit v ccio digital supply current (operating mode) no dc load, v ccio = 3.6 v (8) 10 ma i ccio v ccio digital supply current (standby mode) no dc load, v ccio = 3.6 v (8) 300 m a v ccio digital supply current (halt mode) no dc load, v ccio = 3.6 v (8) 300 m a v ccad supply current (operating mode) all frequencies, v ccad = 3.6 v 15 ma i ccad v ccad supply current (standby mode) all frequencies, v ccad = 3.6 v 20 m a v ccad supply current (halt mode) all frequencies, v ccad = 3.6 v 20 m a v ccp = 3.6 v read operation 55 ma v ccp = 3.6 v program and erase 70 ma v ccp = 3.6 v standby mode i ccp v ccp pump supply current 20 m a operation (7) v ccp = 3.6 v halt mode 20 m a operation (7) c i input capacitance 2 pf c o output capacitance 3 pf (8) i/o pins configured as inputs or outputs with no load. all pulldown inputs 0.2 v. all pullup inputs 3 v ccio ? 0.2 v. a. for these values, see the "electrical characteristics over recommended operating free-air temperature range" table. b. all timing parameters measured using an external load capacitance of 150 pf unless otherwise noted. figure 4. test load circuit 25 submit documentation feedback adv ance informa tion www .ti.com

w where: i ol = i ol max for the respective pin (a) i oh = i oh min for the respective pin (a) v load = 1.5 v c l = 150-pf typical load-circuit capacitance (b)
timing parameter symbology tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 timing parameter symbols have been created in accordance with jedec standard 100. to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: cm compaction, cmpct rd read co clkout rst reset, rst er erase rx scinrx iclk interface clock s slave mode m master mode scc scinclk osc, osci oscin simo spinsimo osco oscout somi spinsomi p program, prog spc spinclk r ready sys system clock r0 read margin 0, rdmrgn0 tx scintx r1 read margin 1, rdmrgn1 lowercase subscripts and their meanings are: a access time r rise time c cycle time (period) su setup time d delay time t transition time f fall time v valid time h hold time w pulse duration (width) the following additional letters are used with these meanings: h high x unknown, changing, or don't care level l low z high impedance v valid 26 submit documentation feedback www .ti.com adv ance informa tion
external reference resonator/crystal oscillator clock option tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 the oscillator is enabled by connecting the appropriate fundamental 4?20 mhz resonator/crystal and load capacitors across the external oscin and oscout pins as shown in figure 5 a. the oscillator is a single-stage inverter held in bias by an integrated bias resistor. this resistor is disabled during leakage test measurement and halt mode. ti strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. the vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes. an external oscillator source can be used by connecting a 1.8-v clock signal to the oscin pin and leaving the oscout pin unconnected (open) as shown in figure 5 b. a. the values of c1 and c2 should be provided by the resonator/crystal vendor. figure 5. crystal/clock connection 27 submit documentation feedback adv ance informa tion www .ti.com ! "

zpll and clock specifications timing requirements for zpll circuits enabled or disabled switching characteristics over recommended operating conditions for clocks (1) (2) tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 min max unit f (osc) input clock frequency 4 20 mhz t c(osc) cycle time, oscin 50 ns t w(oscil) pulse duration, oscin low 15 ns t w(oscih) pulse duration, oscin high 15 ns f (oscrst) osc fail frequency (1) 53 khz (1) causes a device reset (specifically a clock reset) by setting the rst osc fail (glbctrl.15) and the osc fail flag (glbstat.1) bits equal to 1. for more detailed information on these bits and device resets, see the tms470r1x system module reference guide (literature number spnu189). parameter test conditions (3) min max unit pipeline mode enabled 60 mhz f (sys) system clock frequency (4) pipeline mode disabled 24 mhz f (config) system clock frequency flash config mode 24 mhz f (iclk) interface clock frequency 25 mhz pipeline mode enabled 25 mhz f (eclk) external clock output frequency for ecp module pipeline mode disabled 24 mhz pipeline mode enabled 16.7 ns t c(sys) cycle time, system clock pipeline mode disabled 41.6 ns t c(config) cycle time, system clock flash config mode 41.6 ns t c(iclk) cycle time, interface clock 40 ns pipeline mode enabled 40 ns t c(eclk) cycle time, ecp module external clock output pipeline mode disabled 41.6 ns (1) when plldis = 0, f (sys) = m f (osc) /r, where m = {4 or 8}, r = {1,2,3,4,5,6,7,8}. r is the system-clock divider determined by the clkdivpre [2:0] bits in the global control register (glbctrl[2:0]) and m is the pll multiplier determined by the mult4 bit (glbctrl.3). when plldis = 1, f (sys) = f (osc) /r, where r = {1,2,3,4,5,6,7,8}. f (iclk) = f (sys) /x, where x = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. x is the interface clock divider ratio determined by the pcr0[4:1] bits in the sys module. (2) f (eclk) = f (iclk) /n, where n = {1 to 256}. n is the ecp prescale value defined by the ecpctrl[7:0] register bits in the ecp module. (3) pipeline mode enabled or disabled is determined by the enpipe bit (fmregopt.0). (4) flash vread must be set to 5 v to achieve maximum system clock frequency. 28 submit documentation feedback www .ti.com adv ance informa tion
switching characteristics over recommended operating conditions for external clocks (1) (2) (3) tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 (see figure 6 and figure 7 ) parameter test conditions min max unit sysclk or mclk (4) 0.5t c(sys) ? t f t w(col) pulse duration, clkout low iclk: x is even or 1 (5) 0.5t c(iclk) ? t f ns iclk: x is odd and not 1 (5) 0.5t c(iclk) + 0.5t c(sys) ? t f sysclk or mclk (4) 0.5t c(sys) ? t r t w(coh) pulse duration, clkout high iclk: x is even or 1 (5) 0.5t c(iclk) ? t r ns iclk: x is odd and not 1 (5) 0.5t c(iclk) ? 0.5t c(sys) ? t r n is even and x is even or odd 0.5t c(eclk) ? t f t w(eol) pulse duration, eclk low n is odd and x is even 0.5t c(eclk) ? t f ns n is odd and x is odd and not 1 0.5t c(eclk) + 0.5t c(sys) ? t f n is even and x is even or odd 0.5t c(eclk) ? t r t w(eoh) pulse duration, eclk high n is odd and x is even 0.5t c(eclk) ? t r ns n is odd and x is odd and not 1 0.5t c(eclk) ? 0.5t c(sys) ? t r (1) x = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. x is the interface clock divider ratio determined by the pcr0[4:1] bits in the sys module. (2) n = {1 to 256}. n is the ecp prescale value defined by the ecpctrl[7:0] register bits in the ecp module. (3) clkout/eclk pulse durations (low/high) are a function of the oscin pulse durations when plldis is active. (4) clock source bits are selected as either sysclk (clkcntl[6:5] = 11 binary) or mclk (clkcntl[6:5] = 10 binary). (5) clock source bits are selected as iclk (clkcntl[6:5] = 01 binary). figure 6. clkout timing diagram figure 7. eclk timing diagram 29 submit documentation feedback adv ance informa tion www .ti.com

rst and porrst timings timing requirements for porrst switching characteristics over recommended operating conditions for rst (1) tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 (see figure 8 ) min max unit v ccporl v cc low supply level when porrst must be active during power up 0.6 v v cc high supply level when porrst must remain active during power up and become v ccporh 1.5 v active during power down v ccioporl v ccio low supply level when porrst must be active during power up 1.1 v v ccio high supply level when porrst must remain active during power up and become v ccioporh 2.75 v active during power down v il low-level input voltage after v ccio > v ccioporh 0.2 v ccio v v il(porrst) low-level input voltage of porrst before v ccio > v ccioporl 0.5 v t su(porrst)r setup time, porrst active before v ccio > v ccioporl during power up 0 ms t su(vccio)r setup time, v ccio > v ccioporl before v cc > v ccporl 0 ms t h(porrst)r hold time, porrst active after v cc > v ccporh 1 ms t su(porrst)f setup time, porrst active before v cc v ccporh during power down 8 m s t h(porrst)rio hold time, porrst active after v cc > v ccioporh 1 ms t h(porrst)d hold time, porrst active after v cc < v ccporl 0 ms t su(porrst)fio setup time, porrst active before v cc v ccioporh during power down 0 ns t su(vccio)f setup time, v cc < v ccporl before v ccio < v ccioporl 0 ns note: v ccio > 1.1 v before v cc > 0.6 v figure 8. porrst timing diagram parameter min max unit valid time, rst active after porrst inactive 4112t c(osc) t v(rst) ns valid time, rst active (all others) 8t c(sys) flash start up time, from rst inactive to fetch of first instruction from flash (flash pump t fsu 716t c(osc) ns stabilization time) (1) specified values do not include rise/fall times. for rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. 30 submit documentation feedback www .ti.com adv ance informa tion

jtag scan interface timing tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 (jtag clock specification 10-mhz and 50-pf load on tdo output) min max unit t c(jtag) cycle time, jtag low and high period 50 ns t su(tdi/tms - tckr) setup time, tdi, tms before tck rise (tckr) 15 ns t h(tckr -tdi/tms) hold time, tdi, tms after tckr 15 ns t h(tckf -tdo) hold time, tdo after tckf 10 ns t d(tckf -tdo) delay time, tdo valid after tck fall (tckf) 45 ns figure 9. jtag scan timings 31 submit documentation feedback adv ance informa tion www .ti.com

output timings switching characteristics for output timings versus load capacitance (c l ) tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 (see figure 10 ) parameter min max unit c l = 15 pf 0.5 2.5 c l = 50 pf 1.5 5 t r rise time, clkout, awd, tdo ns c l = 100 pf 3 9 c l = 150 pf 4.5 12.5 c l = 15 pf 0.5 2.5 c l = 50 pf 1.5 5 t f fall time, clkout, awd, tdo ns c l = 100 pf 3 9 c l = 150 pf 4.5 12.5 c l = 15 pf 2.5 8 c l = 50 pf 5 14 t r rise time, spinclk, spinsomi, spinsimo (1) ns c l = 100 pf 9 23 c l = 150 pf 13 32 c l = 15 pf 2.5 8 c l = 50 pf 5 14 t f fall time, rst, spinclk, spinsomi, spinsimo (1) ns c l = 100 pf 9 23 c l = 150 pf 13 32 c l = 15 pf 2.5 12 c l = 50 pf 6.0 28 t r rise time, all other output pins ns c l = 100 pf 12 50 c l = 150 pf 18 73 c l = 15 pf 3 12 c l = 50 pf 8.5 28 t f fall time, all other output pins ns c l = 100 pf 16 50 c l = 150 pf 23 73 (1) where n = 1?3. figure 10. cmos-level outputs 32 submit documentation feedback www .ti.com adv ance informa tion

input timings timing requirements for input timings (1) flash timings timing requirements for program flash (1) tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 (see figure 11 ) min max unit t pw input minimum pulse width t c(iclk) + 10 ns (1) t c(iclk) = interface clock cycle time = 1/f (iclk) figure 11. cmos-level inputs min typ max unit t prog(16-bit) half word (16-bit) programming time 4 16 200 m s t prog(total) 512k-byte programming time (2) 4 15 s t erase(sector) sector erase time 1.7 s t wec write/erase cycles at t a = ?40 c to 125 c 50000 cycles t fp( rst) flash pump setting time from rst to sleep 143t c(sys) ns t fp(sleep) initial flash pump setting time from sleep to standby 143t c(sys) ns t fp(stdby) initial flash pump setting time from standby to active 72t c(sys) ns (1) for more detailed information on the flash core sectors, see the flash program and erase section of this data sheet. (2) the 512k-byte programming time includes overhead of state machine. 33 submit documentation feedback adv ance informa tion www .ti.com

spin master mode timing parameters spin master mode external timing parameters tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 (clock phase = 0, spinclk = output, spinsimo = output, and spinsomi = input) (1) (2) (3) (see figure 12 ) no. min max unit 1 t c(spc)m cycle time, spinclk (4) 100 256t c(iclk) ns t w(spch)m pulse duration, spinclk high (clock polarity = 0) 0.5t c(spc)m ? t r 0.5t c(spc)m + 5 2 (5) ns t w(spcl)m pulse duration, spinclk low (clock polarity = 1) 0.5t c(spc)m ? t f 0.5t c(spc)m + 5 t w(spcl)m pulse duration, spinclk low (clock polarity = 0) 0.5t c(spc)m ? t f 0.5t c(spc)m + 5 3 (5) ns t w(spch)m pulse duration, spinclk high (clock polarity = 1) 0.5t c(spc)m ? t r 0.5t c(spc)m + 5 t d(spch-simo)m delay time, spinclk high to spinsimo valid (clock polarity = 0) 10 4 (5) ns t d(spcl-simo)m delay time, spinclk low to spinsimo valid (clock polarity = 1) 10 t v(spcl-simo)m valid time, spinsimo data valid after spinclk low (clock polarity = 0) t c(spc)m ? 5 ? t f 5 (5) ns t v(spch-simo)m valid time, spinsimo data valid after spinclk high (clock polarity = 1) t c(spc)m ? 5 ? t r t su(somi-spcl)m setup time, spinsomi before spinclk low (clock polarity = 0) 6 6 (5) ns t su(somi-spch)m setup time, spinsomi before spinclk high (clock polarity = 1) 6 t v(spcl-somi)m valid time, spinsomi data valid after spinclk low (clock polarity = 0) 4 7 (5) ns t v(spch-somi)m valid time, spinsomi data valid after spinclk high (clock polarity = 1) 4 (1) the master bit (spinctrl2.3) is set and the clock phase bit (spinctrl2.0) is cleared. (2) t c(iclk) = interface clock cycle time = 1/f (iclk) (3) for rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. (4) when the spi is in master mode, the following must be true: for ps values from 1 to 255: t c(spc)m 3 (ps +1)t c(iclk) 3 100 ns, where ps is the prescale value set in the spinctl1[12:5] register bits. for ps values of 0: t c(spc)m = 2t c(iclk) 3 100 ns. (5) the active edge of the spinclk signal referenced is controlled by the clock polarity bit (spinctrl2.1). figure 12. spin master mode external timing (clock phase = 0) 34 submit documentation feedback www .ti.com adv ance informa tion ! "$& ! "$& #$"$ %#$ #$"%$$#

spin master mode external timing parameters tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 (clock phase = 1, spinclk = output, spinsimo = output, and spinsomi = input) (1) (2) (3) (see figure 13 ) no. min max unit 1 t c(spc)m cycle time, spinclk (4) 100 256t c(iclk) ns t w(spch)m pulse duration, spinclk high (clock polarity = 0) 0.5t c(spc)m ? t r 0.5t c(spc)m + 5 2 (5) ns t w(spcl)m pulse duration, spinclk low (clock polarity = 1) 0.5t c(spc)m ? t f 0.5t c(spc)m + 5 t w(spcl)m pulse duration, spinclk low (clock polarity = 0) 0.5t c(spc)m ? t f 0.5t c(spc)m + 5 3 (5) ns t w(spch)m pulse duration, spinclk high (clock polarity = 1) 0.5t c(spc)m ? t r 0.5t c(spc)m + 5 valid time, spinclk high after spinsimo data valid t v(simo-spch)m 0.5t c(spc)m ? 15 (clock polarity = 0) 4 (5) ns valid time, spinclk low after spinsimo data valid t v(simo-spcl)m 0.5t c(spc)m ? 15 (clock polarity = 1) valid time, spinsimo data valid after spinclk high t v(spch-simo)m 0.5t c(spc)m ? 5 ? t r (clock polarity = 0) 5 (5) ns valid time, spinsimo data valid after spinclk low t v(spcl-simo)m 0.5t c(spc)m ? 5 ? t f (clock polarity = 1) t su(somi-spch)m setup time, spinsomi before spinclk high (clock polarity = 0) 6 6 (6) ns t su(somi-spcl)m setup time, spinsomi before spinclk low (clock polarity = 1) 6 valid time, spinsomi data valid after spinclk high t v(spch-somi)m 4 (clock polarity = 0) 7 (6) ns valid time, spinsomi data valid after spinclk low t v(spcl-somi)m 4 (clock polarity = 1) (1) the master bit (spinctrl2.3) is set and the clock phase bit (spinctrl2.0) is set. (2) t c(iclk) = interface clock cycle time = 1/f (iclk) (3) for rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. (4) when the spi is in master mode, the following must be true: for ps values from 1 to 255: t c(spc)m 3 (ps +1)t c(iclk) 3 100 ns, where ps is the prescale value set in the spinctl1[12:5] register bits. for ps values of 0: t c(spc)m = 2t c(iclk) 3 100 ns. (5) the active edge of the spinclk signal referenced is controlled by the clock polarity bit (spinctrl2.1). (6) the active edge of the spinclk signal referenced is controlled by the clock polarity bit (spinctrl2.1). figure 13. spin master mode external timing (clock phase = 1) 35 submit documentation feedback adv ance informa tion www .ti.com $ ! "$& ! "$& #$"$ %#$ #$"%$$#

spin slave mode timing parameters spin slave mode external timing parameters tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 (clock phase = 0, spinclk = input, spinsimo = input, and spinsomi = output) (1) (2) (3) (4) (see figure 14 ) no. min max unit 1 t c(spc)s cycle time, spinclk (5) 100 256t c(iclk) ns t w(spch)s pulse duration, spinclk high (clock polarity = 0) 0.5t c(spc)s ? 0.25t c(iclk) 0.5t c(spc)s + 0.25t c(iclk) 2 (6) ns t w(spcl)s pulse duration, spinclk low (clock polarity = 1) 0.5t c(spc)s ? 0.25t c(iclk) 0.5t c(spc)s + 0.25t c(iclk) t w(spcl)s pulse duration, spinclk low (clock polarity = 0) 0.5t c(spc)s ? 0.25t c(iclk) 0.5t c(spc)s + 0.25t c(iclk) 3 (6) ns t w(spch)s pulse duration, spinclk high (clock polarity = 1) 0.5t c(spc)s ? 0.25t c(iclk) 0.5t c(spc)s + 0.25t c(iclk) t d(spch- delay time, spinclk high to spinsomi valid 6 + t r somi)s (clock polarity = 0) 4 (6) ns t d(spcl- delay time, spinclk low to spinsomi valid 6 + t f somi)s (clock polarity = 1) t v(spch- valid time, spinsomi data valid after spinclk high t c(spc)s ? 6 ? t r somi)s (clock polarity = 0) 5 (6) ns t v(spcl- valid time, spinsomi data valid after spinclk low (clock t c(spc)s ? 6 ? t f somi)s polarity = 1) t su(simo- setup time, spinsimo before spinclk low 6 spcl)s (clock polarity = 0) 6 (6) ns t su(simo- setup time, spinsimo before spinclk high 6 spch)s (clock polarity = 1) t v(spcl- valid time, spinsimo data valid after spinclk low (clock 6 simo)s polarity = 0) 7 (6) ns t v(spch- valid time, spinsimo data valid after spinclk high 6 simo)s (clock polarity = 1) (1) the master bit (spinctrl2.3) is cleared and the clock phase bit (spinctrl2.0) is cleared. (2) if the spi is in slave mode, the following must be true: t c(spc)s 3 (ps + 1) t c(iclk) , where ps = prescale value set in spinctl1[12:5]. (3) for rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. (4) t c(iclk) = interface clock cycle time = 1/f (iclk) (5) when the spin is in slave mode, the following must be true: for ps values from 1 to 255: t c(spc)s 3 (ps +1)t c(iclk) 3 100 ns, where ps is the prescale value set in the spinctl1[12:5] register bits. for ps values of 0: t c(spc)s = 2t c(iclk) 3 100 ns. (6) the active edge of the spinclk signal referenced is controlled by the clock polarity bit (spinctrl2.1). figure 14. spin slave mode external timing (clock phase = 0) 36 submit documentation feedback www .ti.com adv ance informa tion ! "$& ! "$& $ %#$ $#

spin slave mode external timing parameters tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 (clock phase = 1, spinclk = input, spinsimo = input, and spinsomi = output) (1) (2) (3) (4) (see figure 15 ) no. min max uni t 1 t c(spc)s cycle time, spinclk (5) 100 256t c(iclk) ns t w(spch)s pulse duration, spinclk high (clock polarity = 0) 0.5t c(spc)s ? 0.25t c(iclk) 0.5t c(spc)s + 0.25t c(iclk) 2 (6) ns t w(spcl)s pulse duration, spinclk low (clock polarity = 1) 0.5t c(spc)s ? 0.25t c(iclk) 0.5t c(spc)s + 0.25t c(iclk) t w(spcl)s pulse duration, spinclk low (clock polarity = 0) 0.5t c(spc)s ? 0.25t c(iclk) 0.5t c(spc)s + 0.25t c(iclk) 3 (6) ns t w(spch)s pulse duration, spinclk high (clock polarity = 1) 0.5t c(spc)s ? 0.25t c(iclk) 0.5t c(spc)s + 0.25t c(iclk) valid time, spinclk high after spinsomi data valid t v(somi-spch)s 0.5t c(spc)s ? 6 ? t r (clock polarity = 0) 4 (6) ns valid time, spinclk low after spinsomi data valid t v(somi-spcl)s 0.5t c(spc)s ? 6 ? t f (clock polarity = 1) valid time, spinsomi data valid after spinclk high t v(spch-somi)s 0.5t c(spc)s ? 6 ? t r (clock polarity = 0) 5 (6) ns valid time, spinsomi data valid after spinclk low t v(spcl-somi)s 0.5t c(spc)s ? 6 ? t f (clock polarity = 1) setup time, spinsimo before spinclk high t su(simo-spch)s 6 (clock polarity = 0) 6 (6) ns setup time, spinsimo before spinclk low t su(simo-spcl)s 6 (clock polarity = 1) valid time, spinsimo data valid after spinclk high t v(spch-simo)s 6 (clock polarity = 0) 7 (6) ns valid time, spinsimo data valid after spinclk low t v(spcl-simo)s 6 (clock polarity = 1) (1) the master bit (spinctrl2.3) is cleared and the clock phase bit (spinctrl2.0) is set. (2) if the spi is in slave mode, the following must be true: t c(spc)s 3 (ps + 1) t c(iclk) , where ps = prescale value set in spinctl1[12:5]. (3) for rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. (4) t c(iclk) = interface clock cycle time = 1/f (iclk) (5) when the spin is in slave mode, the following must be true: for ps values from 1 to 255: t c(spc)s 3 (ps +1)t c(iclk) 3 100 ns, where ps is the prescale value set in the spinctl1[12:5] register bits. for ps values of 0: t c(spc)s = 2t c(iclk) 3 100 ns. (6) the active edge of the spinclk signal referenced is controlled by the clock polarity bit (spinctrl2.1). 37 submit documentation feedback adv ance informa tion www .ti.com
tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 figure 15. spin slave mode external timing (clock phase = 1) 38 submit documentation feedback www .ti.com adv ance informa tion $ ! "$& ! "$& $%#$ $#

scin isosynchronous mode timings internal clock timing requirements for internal clock scin isosynchronous mode (1) (2) (3) tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 (see figure 16 ) (baud + 1) (baud + 1) uni is even or baud = 0 is odd and baud 1 0 t min max min max cycle time, t c(scc) 2t c(iclk) 2 24 t c(iclk) 3t c(iclk) (2 24 ? 1) t c(iclk) ns scinclk pulse duration, t w(sccl) 0.5t c(scc) ? t f 0.5t c(scc) + 5 0.5t c(scc) + 0.5t c(iclk) ? t f 0.5t c(scc) + 0.5t c(iclk) ns scinclk low pulse duration, t w(scch) 0.5t c(scc) ? t r 0.5t c(scc) + 5 0.5t c(scc) - 0.5t c(iclk) ? t r 0.5t c(scc) ? 0.5t c(iclk) ns scinclk high delay time, t d(scch-txv) scinclk high to 10 10 ns scintx valid valid time, scintx data t v(tx) t c(scc) ? 10 t c(scc) ? 10 ns after scinclk low setup time, t su(rx-sccl) scinrx before t c(iclk) + t f + 20 t c(iclk) + t f + 20 ns scinclk low valid time, scinrx data t v(sccl-rx) ?t c(iclk) + t f + 20 ?t c(iclk) + t f + 20 ns after scinclk low (1) baud = 24-bit concatenated value formed by the sci[h,m,l]baud registers. (2) t c(iclk) = interface clock cycle time = 1/f (iclk) (3) for rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. a. data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous mode. data transmission occurs on the sciclk rising edge, and data reception occurs on the sciclk falling edge. figure 16. scin isosynchronous mode timing diagram for internal clock 39 submit documentation feedback adv ance informa tion www .ti.com

scin isosynchronous mode timings external clock timing requirements for external clock scin isosynchronous mode (1) (2) tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 (see figure 17 ) min max unit t c(scc) cycle time, scinclk (3) 8t c(iclk) ns t w(scch) pulse duration, scinclk high 0.5t c(scc) ? 0.25t c(iclk) 0.5t c(scc) + 0.25t c(iclk) ns t w(sccl) pulse duration, scinclk low 0.5t c(scc) ? 0.25t c(iclk) 0.5t c(scc) + 0.25t c(iclk) ns t d(scch-txv) delay time, scinclk high to scintx valid 2t c(iclk) + 12 + t r ns t v(tx) valid time, scintx data after scinclk low 2t c(scc) ? 10 ns t su(rx-sccl) setup time, scinrx before scinclk low 0 ns t v(sccl-rx) valid time, scinrx data after scinclk low 2t c(iclk) + 10 ns (1) t c(iclk) = interface clock cycle time = 1/f (iclk) (2) for rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table. (3) when driving an external scinclk, the following must be true: t c(scc) 3 8t c(iclk) . a. data transmission / reception characteristics for isosynchronous mode with external clocking are similar to the asynchronous mode. data transmission occurs on the sciclk rising edge, and data reception occurs on the sciclk falling edge. figure 17. scin isosynchronous mode timing diagram for external clock 40 submit documentation feedback www .ti.com adv ance informa tion

high-end timer (het) timings minimum pwm output pulse width: minimum input pulses that can be captured: high-end can controller (heccn) mode timings dynamic characteristics for the cannhtx and cannhrx pins tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 this is equal to one high resolution clock period (hrp). the hrp is defined by the 6-bit high resolution prescale factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes. therefore, the minimum pwm output pulse width = hrp(min) = hr(min)/sysclk = 1/sysclk for example, for a sysclk of 30 mhz, the minimum pwm output pulse width = 1/30 = 33.33ns the input pulse width must be greater or equal to the low resolution clock period (lrp), i.e., the het loop (the het program must fit within the lrp). the lrp is defined by the 3-bit loop-resolution prescale factor (lr), which is user defined, with a power of 2 increment of codes. that is, the value of lr can be 1, 2, 4, 8, 16, or 32. therefore, the minimum input pulse width = lrp(min) = hr(min) * lr(min)/sysclk = 1 * 1/sysclk for example, with a sysclk of 30 mhz, the minimum input pulse width = 1 * 1/30 = 33.33 ns note: once the input pulse width is greater than lrp, the resolution of the measurement is still hrp. (that is, the captured value gives the number of hrp clocks inside the pulse.) abbreviations: hr = het high resolution divide rate = 1, 2, 3,...63, 64 lr = het low resolution divide rate = 1, 2, 4, 8, 16, 32 high resolution clock period = hrp = hr/sysclk loop resolution clock period = lrp = hr*lr/sysclk parameter min max unit t d(cannhtx) delay time, transmit shift register to cannhtx pin (1) 15 ns t d(cannhrx) delay time, cannhrx pin to receive shift register 5 ns (1) these values do not include rise/fall times of the output buffer. 41 submit documentation feedback adv ance informa tion www .ti.com
multi-buffered a-to-d converter (mibadc) tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 the multi-buffered a-to-d converter (mibadc) has a separate power bus for its analog circuitry that enhances the a-to-d performance by preventing digital switching noise on the logic circuitry, which could be present on v ss and v cc , from coupling into the a-to-d analog stage. all a-to-d specifications are given with respect to ad reflo unless otherwise noted. resolution 10 bits (1024 values) monotonic assured output conversion code 00h to 3ffh [00 for v ai ad reflo ; 3ff for v ai 3 ad refhi ] table 10. mibadc recommended operating conditions (1) min max unit ad refhi a-to-d high-voltage reference source v ssad v ccad v ad reflo a-to-d low-voltage reference source v ssad v ccad v v ai analog input voltage v ssad ? 0.3 v ccad + 0.3 v analog input clamp current (2) i aic ?2 2 ma (v ai < v ssad ? 0.3 or v ai > v ccad + 0.3) (1) for v ccad and v ssad recommended operating conditions, see the "device recommended operating conditions" table. (2) input currents into any adc input channel outside the specified limits could affect conversion results of other channels. table 11. operating characteristics over full ranges of recommended operating conditions (1) (2) parameter description/conditions min typ max unit r i analog input resistance see figure 18 . 250 500 w conversion 10 pf c i analog input capacitance see figure 18 . sampling 30 pf i ail analog input leakage current see figure 18 . ?1 1 m a i adrefhi ad refhi input current ad refhi = 3.6 v, ad reflo = v ssad 5 ma conversion range over which specified cr ad refhi - ad reflo 3 3.6 v accuracy is maintained difference between the actual step width e dnl differential nonlinearity error 1.5 lsb and the ideal value. see figure 19 . maximum deviation from the best straight line through the mibadc. mibadc e inl integral nonlinearity error 2 lsb transfer characteristics, excluding the quantization error. see figure 20 . maximum value of the difference e tot total error/absolute accuracy between an analog value and the ideal 2 lsb midstep value. see figure 21 . (1) v ccad = ad refhi (2) 1 lsb = (ad refhi ? ad reflo )/ 2 10 for the mibadc 42 submit documentation feedback www .ti.com adv ance informa tion
multi-buffer adc timing requirements tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 figure 18. mibadc input equivalent circuit min nom max unit t c(adclk) cycle time, mibadc clock 0.05 m s t d(sh) delay time, sample and hold time 1 m s t d?) delay time, conversion time 0.55 m s t d(shc) (1) delay time, total sample/hold and conversion time 1.55 m s (1) this is the minimum sample/hold and conversion time that can be achieved. these parameters are dependent on many factors; for more details, see the tms470r1x multi-buffered analog-to-digital converter (mibadc) reference guide (literature number spnu206). the differential nonlinearity error shown in figure 19 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 lsb. a. 1 lsb = (ad refhi - ad reflo )/2 10 figure 19. differential nonlinearity (dnl) 43 submit documentation feedback adv ance informa tion www .ti.com

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tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 the integral nonlinearity error shown in figure 20 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line. a. 1 lsb = (ad refhi - ad reflo )/2 10 figure 20. integral nonlinearity (inl) error the absolute accuracy or total error of an mibadc as shown in figure 21 is the maximum value of the difference between an analog value and the ideal midstep value. a. 1 lsb = (ad refhi - ad reflo )/2 10 figure 21. absolute accuracy (total) error 44 submit documentation feedback www .ti.com adv ance informa tion
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thermal resistance characteristics tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 parameter c/w r q ja 43 r q jc 6.5 45 submit documentation feedback adv ance informa tion www .ti.com
tms470r1b512 16/32-bit risc flash microcontroller spns107a ? september 2005 ? revised august 2006 revision history this revision history highlights the changes made to the device-specific datasheet spns107. table 12. revision history spns107 to spns107a revised the family nomenclature drawing to add q version of the temperature range. revised "absolute maximum ratings" table to add q version of the temperature range. revised "device recommended operating conditions" table to add q version of the temperature range. added note to porrst timing diagram. changed t a range to ?40 c to 125 c on t wec in "timing requirements for program flash" table. added t wec min value of 50000 and deleted max value in "timing requirements for program flash" table. changed t erase(sector) typ value to 1.7 and removed max value in "timing requirements for program flash" table. 46 submit documentation feedback www .ti.com adv ance informa tion
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) TMP470R1B512pge preview lqfp pge 144 1 tbd call ti call ti tms470r1b512pget active lqfp pge 144 60 green (rohs & no sb/br) cu nipdau level-3-260c-168hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 28-jun-2006 addendum-page 1
mechanical data mtqf017a october 1994 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pge (s-pqfp-g144) plastic quad flatpack 4040147 / c 10/96 0,27 72 0,17 37 73 0,13 nom 0,25 0,75 0,45 0,05 min 36 seating plane gage plane 108 109 144 sq sq 22,20 21,80 1 19,80 17,50 typ 20,20 1,35 1,45 1,60 max m 0,08 0 7 0,08 0,50 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
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